For faster computational chips, manufacturers have been increasing the chips’ computational power by giving them additional cores. For instance – a typical chip may feature six or eight cores, but only one pair of core can work at a time, this means there is a limitation to chips, even if a chip has 100 to 1000 cores. An associate professor of electrical engineering and computer science at
MIT, Li-Shiuan Peh has been looking forward at the cores to communicate in a similar way that a computer with Internet does. The research team has been working on techniques to increase computational speed with low power consumption. By transmitting information into ‘packets’ and each core would have its own router, enabling sending packet down any of several paths, depending on the condition of the network as a whole. Peh and the colleagues will be showcasing this paper called ‘summarizing 10 years of research’ on such ‘networks on chip.’
“Buses have hit a limit,” Peh says. “They typically scale to about eight cores.” The 10-core chips found in high-end servers frequently add a second bus, but that approach won’t work for chips with hundreds of cores. She further explains, “buses take up a lot of power, because they are trying to drive long wires to eight or 10 cores at the same time.” In the type of network Peh is proposing, on the other hand, each core communicates only with the four cores nearest it. “Here, you’re driving short segments of wires, so that allows you to go lower in voltage.”
A packet of data traveling from one core to another has to stop at every router in between, one of them is stored in memory while the other is handled by router. Apparently, engineers worry that these added requirements will introduce enough delays and computational complexity to offset the advantages of packet switching. “The biggest problem, I think, is that in industry right now, people don’t know how to build these networks, because it has been buses for decades,” Peh says.
These researchers have developed two techniques to address these problems – virtual bypassing and low-signal signaling. In the first technique, a packet arrives at a router and the router looks into the addressing information before deciding the path and sending it. Each router sends an advance signal to the next, it presets the switch and speeds the packet with no additional computation. In the low-swing signaling technique, digital data consists of ones and zeroes, which are transmitted over communications channels as high and low voltages. A PhD student has developed a circuit that reduces the swing between the high and low voltages from one volt to 300 millivolts. The combination of virtual bypassing and low-swing signaling, resulted into the chip consuming 38 percent less energy than previous packet-switched test chips. Although there is more work on it, Peh said, “if we compare it against a bus, we get orders-of-magnitude savings.”
Luca Carloni, an associate professor of computer science at Columbia University who also researches networks on chip, says “the jury is always still out” on the future of chip design, but that “the advantages of packet-switched networks on chip seem compelling.”
